?2004 device engineering inc page 1 of 8 ds-mw-01073-01 rev c 05/31/2005 features ? ttl/cmos to arinc 429 line driver. ? rate control input set hi (100kbs) or lo (12.5kbs) speed slew rates. ? operates from 9.5v to 16.5v power supply. ? drives full arinc load. ? output resistor options: 0, 10 or 37.5 ohms. ? tristate outputs ? thermally enhanced 8 lead soic package. ? outputs short circuit tolerant general description the DEI1073 family of 8 pin bicmos integrated circuits are line drivers designed to directly drive the arinc 429 avionics serial digital data bus. the device converts ttl/cmos serial input data to the tri-level rz bipolar differential modulation format of the arinc bus. the outputs are tri-state capable. a ttl/cmos control inpu t selects the output slew rate for hi (100kbs) and low (12.5kbs) speed operation. no external timing capacitors are required. the DEI1073 has internal 37.5 ohm output resistors, the dei1074 has 10 ohm resistors, and the dei1075 has none. the 10 and 0 ohm options require external series resistors which ar e typically used to implement a transient voltage protection network. table 1 pin description 8 7 6 5 1 2 3 4 hi/lo ttlin0 ttlin1 gnd v- 429outa 429outb v+ pin name description 1 hi/lo logic input. slew rate control. 1 = hi speed. 0 = low speed. 2 ttlin0 logic input. serial digital data input 0. 3 ttlin1 logic input. serial digital data input 1. 4 gnd power input. ground. 5 v- power input. ?9.5 to ?16.5 vdc 6 429outa 429 output. arinc 429 format seri al digital data output a. 7 429outb 429 output. arinc 429 format seri al digital data output b. 8 v+ power input. +9.5 to +16.5 vdc. note: heatsink pad is electrically isolated. 385 east alamo drive chandler, az 85225 phone: (480) 303-0822 fax: (480) 303-0824 e - mail: admin@deiaz.com DEI1073, dei1074, dei1075 arinc 429 line driver with rate select and tri-state d evice e ngineering incorporated
?2004 device engineering inc page 2 of 8 ds-mw-01073-01 rev c 05/31/2005 functional description input logic and level shift edge shaping output drivers 429outa 429outb hi/lo ttlin1 ttlin0 tri-state block diagram table 2 speed control function table hi/lo output transition time 0 10us (12.5 kbs data) 1 1.5us (100kbs data) table 3 transmit data function table ttlin1 ttlin0 429outa 429outb notes 0 0 0v 0v null output 0 1 -5v 5v zero output 1 0 5v -5v one output 1 1 hi-z hi-z tri-state output ttlin1 ttlin0 429outa 429outb +5 -5 +5 -5 differential 429out (a-b) +10 -5 tskew 50% 50% trise trise tfall tfall 90% 10% 10% 90% line driver waveforms
?2004 device engineering inc page 3 of 8 ds-mw-01073-01 rev c 05/31/2005 electrical description table 4 absolute maximum ratings parameter voltages referenced to ground min max units v+ supply voltage -0.3 +20 v v1- supply voltage 0.3 -20 v v+, v- supply slew rate +/-100 v/us storage temperature -65 +150 c input voltage ttlin and hi/lo inputs 429out outputs gnd ? 0.3 ?v-? ? 0.3 ?v+? + 0.3 ?v+? + 0.3 v v power dissipation @ 85 c: (> 10 sec) 8 lead eq soic, thermal pad soldered to heat spreader land, 1.0 w junction temperature: tjmax, plastic packages (limited by molding compound tg) tjmax, ceramic packages 145 160 c c esd per jedec a114-a human body model 2000 v lead soldering temperature (10 sec duration) 280 c notes: 1. stresses above absolute maximum ratings may cause permanent damage to the device. 2. the device is tolerant of one or both outputs shorted to ground and of both outputs sh orted together. table 5 recommended operating conditions parameter symbol conditions supply voltage v+ v- 9.5 to 16.5v -9.5 to ?16.5v operating temperature plastic package ceramic packages t op -55 to +85 c or -55 to +125 c
?2004 device engineering inc page 4 of 8 ds-mw-01073-01 rev c 05/31/2005 table 6 electrical characteristics conditions : tcase = rated operating temperature -55/+85c or -55/+125c v+/- = +/-9.5 to +/-16.5v unless otherwise noted. parameter test condition symbol min nom max units logic inputs input voltage, logic 1 v ih 2.0 v+ v input voltage, logic 0 v il -0.3 0.8 v input current, logic 1 vin = 5.0v i ih 0 100 ua input current, logic 0 vin = 0.0v i il 0 -100 ua arinc outputs a rinc output voltage (differential) one null zero differential output voltage = 429outa ? 429outb. no load. v dif1 v difnull v dif0 9.0 -0.5 -9.0 10.0 0 -10.0 11.0 +0.5 -11.0 v v v a rinc output voltage (single ended) hi null lo referenced to ground no load. vo hi vo null, vo lo 4.5 -0.25 -5.5 5.0 0 -5.0 5.5 +0.25 -4.5 v v v output tristate current -5v to +5v iz -10 +10 ua arinc output short circuit current outputs shorted to ground. isc lo isc hi 130 -130 ma ma output resistance: DEI1073 dei1074 dei1075 room temperature rout37 rout10 rout0 37.5 10 0 ohms ohms ohms output slew rate, hi speed lo to hi and hi to lo transitions hi/lo = 1 n o load 10% to 90% voltage amplitude of differential output. t hi 1.0 2.0 us output slew rate, lo speed lo to hi and hi to lo transitions hi/lo = 0 n o load measured from 10% to 90% voltage amplitude of differential output. t lo 5 15 us output skew time between a and b outputs. hi/lo = 1 measured at 50% voltage amplitude of both outputs tskew 200 ns supply current quiescent operating supply current: iv+ iv- v+ =15v, v- = -15v hi/lo = 0 or 1 ttlin0=ttlin1= 0v no load i v+ i v- - -14.0 6.0 -6.0 14.0 - ma ma
?2004 device engineering inc page 5 of 8 ds-mw-01073-01 rev c 05/31/2005 design considerations transient voltage protection external transient voltage suppressing devices are required to protect the device from stress such as that defined by do160d section 22, lightning induced transient susceptibility. the output stage of the driver includes intrinsic clamp diodes to the v+ and v- power rails. consider using th e 0 ohm output option to allow use of an external 36 ohm current limiting resistor and transient voltage suppressor. transients at the device must be limited to less than one diode drop beyond the power rails to prevent excessive current to the device. thermal management device power dissipation varies greatly as a function of data rate , load capacitance, data duty cycle, and supply voltage. pro per thermal management is important in designs operating at the hi speed data rate (100kbs) with high capacitive loads and high data duty cycles. dissipation may be estimated from the graph below which shows the approximate power dissipation for various loads and supply voltages. it is calculated for 100% da ta duty cycle at 100kbs with no word gap null times and must be reduced by the appropriate data duty cycle. adjust for the ap plication data duty cycle using a factor of (total bits transm itted in 10 sec period / 1,000,000) = (32 x total arinc words transmitted in 10 sec period / 1,000,000). heat transfer from the ic package should be maximized. use maximum trace width on all power and signal connections at the ic. the exposed heat sink pad of the soic package should be soldered to a heat spreader land on the pcb. the pad is electrically isolated. maximize land size by extending beyond the ic outline if po ssible. place vias on the signal/power trac es close to the ic and on the heat spreader land to maximize heat fl ow to the internal power planes. 429 driver device power dissipation (100kbs, 100% dc) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 7 8 9 10 11 12 13 14 15 16 supply voltage (+ / - v) power dissipation (w) 100khz, full load (30nf/400ohm) 100khz, 2/3 load (20nf/600ohm) 100khz, 1/3 load (10nf/1200ohm)
?2004 device engineering inc page 6 of 8 ds-mw-01073-01 rev c 05/31/2005 package description 8 lead edquad soic 0.170 0.070 0.024 0.310 solder mask .136 x .100 copper land with vias to internal plane. large as possible. 0.050 solder stencil: approximately size of exposed pad, depending on solder process exposed pad outline .106 x .070 suggested land pattern (dimensions in inches) table 7 8 lead edquad soic characteristics symbol description value units theta ja junction to ambient. 4 layer board with 2 internal power planes. exposed pad soldered to pcb heat spreader land. 59 c/w msl jedec moisture sensitivity level peak body temperature 2 235 - c e 7 typ. 7 typ. 7 typ. 7 typ. e1 1) all dimensions in millimeter. a1 top view stand-off exposed heatsink seating plane side view bottom view exposed heatsink 2.70.10 1.70.10 r0.50(4x) e e1 d b ddd m c a a2 c ccc -c- detail x 4.67.040 8 1.60 0.05 1.40 4.90 6.00 3.90 0.60 0.10 0.10 1.27 0 ~ 8d 0.20 r 0 b e ddd ccc l e1 e d a2 a1 a dims. max. basic max. max. .15 .10 .20 .10 .10 .05 max. n tols. 0.43 2) reference jedec spec: ms-012 between "seating plane" and the notes: package which ever is lower. r1 typ. 0.13 .05 lead coplanarity seating plane .203mm (0.008") thick.
?2004 device engineering inc page 7 of 8 ds-mw-01073-01 rev c 05/31/2005 8 lead ceramic sidebrazed dip symbol description value units theta jc junction to case 55 c/w theta ja junction to ambient. 125 c/w
?2004 device engineering inc page 8 of 8 ds-mw-01073-01 rev c 05/31/2005 table 3 process flow process step standard burn-in pre-burn-in electrical test n/a yes burn in (1) n/a 96hrs @ +125 c final electrical test, room temperature 100% 100% final electrical test, high temperature 100% @ +85 or +125c 100% @ +85 or +125c final electrical test, low temperature 0.65% aql @ -55c 0.65% aql @ -55c notes: 1. burn-in conditions: 125c, 96 hrs, v+/v- = +/-15.0v inputs = 0v, outputs open. ordering information table 8 ordering information part number marking package output resistor burn-in temperature DEI1073-ses DEI1073 / ses 8l eq soic 37 no -55 / +85 oc dei1074-ses dei1074 / ses 8l eq soic 10 no -55 / +85 oc dei1075-ses dei1075 / ses 8l eq soic 0 no -55 / +85 oc DEI1073-smb DEI1073 / smb 8l eq soic 37 yes -55 / +125 oc dei1074-smb dei1074 / smb 8l eq soic 10 yes -55 / +125 oc dei1075-smb dei1075 / smb 8l eq soic 0 yes -55 / +125 oc DEI1073-dms DEI1073 / dms 8l sb dip 37 no -55 / +125 oc dei1074-dms dei1074 / dms 8l sb dip 10 no -55 / +125 oc dei1075-dms dei1075 / dms 8l sb dip 0 no -55 / +125 oc DEI1073-dmb DEI1073 / dmb 8l sb dip 37 yes -55 / +125 oc dei1074-dmb dei1074 / dmb 8l sb dip 10 yes -55 / +125 oc dei1075-dmb dei1075 / dmb 8l sb dip 0 yes -55 / +125 oc DEI1073-sms DEI1073 / sms 8l eq soic 37 no -55 / +125 oc dei1074-sms dei1074 / sms 8l eq soic 10 no -55 / +125 oc dei1075-sms dei1075 / sms 8l eq soic 0 no -55 / +125 oc dei reserves the right to make changes to any products or sp ecifications herein. dei makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.
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